october 2013 docid025293 rev 1 1/4 ST33G1M2 secure mcu with 32-bit arm? securcore? sc300? cpu and high-density flash memory data brief features hardware features ? arm? securcore? sc300? 32-bit risc core cadenced at 25 mhz ? 30 kbytes of user ram ? up to 1280 kbytes of user flash memory with otp area ? asynchronous receiver transmitter supporting iso/iec 7816-3 t=0 and t=1 protocols (slave mode supported) ? single wire protocol (swp) interface for communications with nfc router (etsi 102-613 compliant) ? serial peripheral interface (spi) master/slave interface ? three 16-bit timers with interrupt capability ? seven general purpose i/os enabling proprietary protocol implementation ? 1.8 v, 3 v and 5 v supply voltage ranges ? external clock frequency from 1 up to 10 mhz ? current consumption compatible with gsm and etsi specifications ? power-saving standby state ? contact assignment compatible with iso/iec 7816-2 ? esd protection greater than 4 kv (hbm) software features ? secure flash loader ? flash drivers ? mifare? libraries: classic, desfire ev1, and plus security features ? active shield ? memory protection unit (mpu) ? monitoring of environmental parameters ? protection against faults ? 16- and 32-bit crc calculation block (iso 13239, ieee 802.3, etc.) ? true random number generator ? unique serial number on each die ? hardware security-enhanced des accelerator ? hardware security-enhanced aes accelerator ? mifare classic? cryptography hardware accelerator ? nescrypt coprocessor for public key cryptography algorithm applications ST33G1M2 major applications include: ? mobile communications (gsm, 3g and cdma) ? java card applications ? multimedia www.st.com free datasheet http:///
description ST33G1M2 2/4 docid025293 rev 1 1 description the ST33G1M2 is a serial access microcontroller designed for secure mobile applications that incorporates the most recent generation of arm processors for embedded secure systems. its securcore? sc300? 32-bit risc core is built on the cortex? m3 core with additional security features to help to protect against advanced forms of attacks. the sc300? core brings great performance and excellent code density thanks to the thumb?-2 instruction set. the high-speed embedded flash memory introduces more flexibility to the system. the ST33G1M2 also offers a serial communication interface fully compatible with the iso/iec 7816-3 standard (t=0, t=1) and a single-wire protocol (swp) interface for communication with a near field communication (nfc) router in sim/nfc applications. an spi master/slave interface is also available for communication in non-sim applications. the ST33G1M2 features hardware accelerators for advanced cryptographic functions. the edes peripheral provides a secure des (data encryption standard) algorithm implementation, while the nescrypt crypto-processor efficiently supports the public key algorithm. the aes peripheral ensures secure and fast aes algorithm implementation. the st33g family operates in the ?25 to +85c temperature range and 1.8v, 3v and 5v supply voltage ranges. a comprehensive range of power-saving modes enables the design of efficient low-power applications. software development tools description dedicated securcore? sc300? software development tools are provided by arm and keil. this includes the instruction set simulator (iss) and c compiler. the documentation is available on the arm and keil web sites. moreover, stmicroelectronics provides: ? a time-accurate hardware emulator controlled by the keil debugger and the stmicroelectronics development environment. ? a complete product simulator based on keil?s iss simulator for the securcore? sc300? cpu. ? a secured romed flash loader with very high-speed software downloading capabilities. note: for mifare library usage, please, refer to the st33g system rom user manual . free datasheet http:///
docid025293 rev 1 3/4 ST33G1M2 revision history 2 revision history table 1. document revision history date revision changes 01-oct-2013 1 initial release. free datasheet http:///
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